Fa
  • Ph.D. (2018)

    Digital Systems

    Electrical and Computer Engineering, University of Tehran, Tehran, Iran

  • M.Sc. (2013)

    Electrical Engineering - Electronics

    , Iran University of Science and Technology, Tehran, Iran

  • Embedded machine learning
  • Internet of Things
  • Brain-inspired computing
  • Robust and energy-efficient system design
  • Hardware implementation of advanced neural networks on FPGA
  • Hardware Security
  • Computer Architecture and Dependable Systems (CADS-Lab)

    Research field:

    Expert:

    Phone: 82883302

    Address:

Omid Akbari received the B.Sc. degree from the University of Guilan, Rasht, Iran, in 2011, the M.Sc. degree from Iran University of Science and Technology, Tehran, Iran, in 2013, and the Ph.D. degree from the University of Tehran, Iran, in 2018, all in Electrical Engineering, Electronics - Digital Systems sub-discipline. He was a visiting researcher in the CARE-Tech Lab. at Vienna University of Technology (TU Wien), Austria, from Apr. to Oct. 2017, and a visiting research fellow under the Future Talent Guest Stay program at Technische Universität Darmstadt (TU Darmstadt), Germany, from Jul. to Sep. 2022. He is currently an assistant professor of Electrical and Computer Engineering at Tarbiat Modares University, Tehran, Iran, where he is also the Director of the Computer Architecture and Dependable Systems Laboratory (CADS-Lab). His current research interests include embedded machine learning, reconfigurable computing, energy-efficient computing, distributed learning, and fault-tolerant system design. For more info about the CADS-Lab please see www.cadslab.ir

Contact

Curriculum Vitae (CV)

2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39

M Abdelsalam, A Abdipour, J Abella, H Aboushady, T Adegbija, K Afrooz, A Afzali-Kusha, J Aghassi-Hagmann, H Aghilinasab, G Agosta, H Ahmad, D Ahn, J Ahn, P Ajay, O Akbari, K Akesson, M Al-Daloo, BM Al-Hashimi, SA Albahrani, MM Ali, W Ali, MA Alim
Journal PaperIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Volume 39 , Issue 12, 2020 December , {Pages }

Abstract

This index covers all technical items—papers, correspondence, reviews, etc.—that appeared in this periodical during 2020, and items from previous years that were commented upon or corrected in 2020. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbrevia- tion, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, mo

2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67

Y Abadi, M Abdel-Aty, A Abdipour, S Abdullah, LF Abdulrazak, H Abdzadeh-Ziabari, S Abolhassani, M Aboudina, H Aboushady, MA Abouzied, A Abusleme, B Acar, A Acharyya, B Adineh, V Afonso, K Afrooz, A Afzali-Kusha, E Aggrawal, B Agnus, L Agostini, A Agrawal,
Journal PaperIEEE Transactions on Circuits and Systems II: Express Briefs , Volume 67 , Issue 12, 2020 December , {Pages }

Abstract

This index covers all technical items—papers, correspondence, reviews, etc.—that appeared in this periodical during 2020, and items from previous years that were commented upon or corrected in 2020. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbrevia- tion, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, mo

X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture

Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Muhammad Shafique
Journal PaperIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2019 August 27, {Pages }

Abstract

Coarse-Grained Reconfigurable Architectures (CGRAs) offer a tradeoff between the flexibility of General Purpose Processors (GPPs) and the performance and energy efficiency of Application Specific Integrated Circuits (ASICs). Hence, these CGRAs are used as an appealing platform to accelerate the compute-intensive applications, especially the streaming-based applications such as multimedia processing and signal processing. However, most of these streaming applications are inherently errorresilient, while state-of-the-art CGRAs only support exact computations. In this paper, we present an energy-efficient Approximate Coarse-Grained Reconfigurable Architecture (XCGRA). Instead of conventional exact arithmetic units, it employs configurable appr

Block-based Carry Speculative Approximate Adder for Energy-Efficient Applications

Farhad Ebrahimi-Azandaryani, Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram
Journal PaperIEEE Transactions on Circuits and Systems II: Express Briefs , 2019 February 22, {Pages }

Abstract

In this paper, a low energy consumption block-based carry speculative approximate adder is proposed. Its structure is based on partitioning the adder into some non-overlapped summation blocks whose structures may be selected from both the carry propagate and parallel-prefix adders. Here, the carry output of each block is speculated based on the input operands of the block itself and those of the next block. In this adder, the length of the carry chain is reduced to two blocks (worst case), where in most cases only one block is employed to calculate the carry output leading to a lower average delay. In addition, to increase the accuracy and reduce the output error rate, an error detection and recovery mechanism is proposed. The effectiveness

PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture

Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Muhammad Shafique
Conference Paper2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) , 2018 March 19, {Pages 413-418 }

Abstract

Coarse-Grained Reconfigurable Architectures (CGRAs) provide tradeoff between the energy-efficiency of Application Specific Integrated Circuits (ASICs) and the flexibility of General Purpose Processors (GPPs). State-of-the-art CGRAs only support exact architectures and precise application executions. However, a majority of the streaming applications such as multimedia and digital signal processing, which are amenable to CGRAs, are inherently error resilient. Therefore, these applications can greatly benefit from the emerging trend of Approximate Computing that leverages this error-resiliency to provide higher energy efficiency proportional to the tolerable accuracy loss (can even be constrained). This paper, for the first time, introduces th

Energy and reliability improvement of voltage-based, clustered, coarse-grain reconfigurable architectures by employing quality-aware mapping

Hassan Afzali-Kusha, Omid Akbari, Mehdi Kamal, Massoud Pedram
Journal PaperIEEE Journal on Emerging and Selected Topics in Circuits and Systems , Volume 8 , Issue 3, 2018 July 17, {Pages 480-493 }

Abstract

An energy-quality scalable coarse grain reconfigurable architecture (CGRA) based on the voltage overscaling (VOS) technique is presented. The approximation level of each processing element (PE) in the CGRA is determined by the applied VOS-determined voltage level. By employing the technique, the architecture may be configured for accurate or approximate modes of computation depending on a user-specified output quality-of-service target for a given application. More precisely, operating voltages used for performing various operations in the application dataflow graph are minimized subject to the output quality constraint by using an energy-quality tradeoff algorithm. To make the hardware implementation of the scheme more efficient, PEs are c

Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures

Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Muhammad Shafique
Journal PaperIEEE Micro , Volume 38 , Issue 6, 2018 October 9, {Pages 63-72 }

Abstract

This paper presents a methodology for designing an approximate coarse-grained reconfigurable architecture (X-CGRA), and its use for accelerating both error-resilient and error-sensitive applications. The output quality of the X-CGRA is manageable at the run-time for better performance and power/energy consumption tradeoffs. Results show up to 1.9? speedup and 2.3? lower energy consumption at the cost of 9.7% accuracy loss for the studied applications.

Energy consumption and lifetime improvement of coarse-grained reconfigurable architectures targeting low-power error-tolerant applications

Hassan Afzali-Kusha, Omid Akbari, Mehdi Kamal, Massoud Pedram
Conference PaperProceedings of the 2018 on Great Lakes Symposium on VLSI , 2018 May 30, {Pages 431-434 }

Abstract

In this work, the application of a voltage over-scaling (VOS) technique for improving the lifetime and reliability of coarse-grained reconfigurable architectures (GCRAs) is presented. The proposed technique, which may be applied to CGRAs used as accelerators for low-power, error-tolerant applications, reduces the (strongly voltage-dependent) wearout effects and the energy consumption of processing elements (PEs) whenever the error impact on the output quality degradation can be tolerated. This provides us with the ability to lessen the wearout and reduce energy consumption of PEs when accuracy requirement for the results is rather low. Multiple degrees of computational accuracy can be achieved by using different overscaled voltage levels fo

Dual-quality 4: 2 compressors for utilizing in dynamic accuracy configurable multipliers

Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram
Journal PaperIEEE Transactions on Very Large Scale Integration (VLSI) Systems , Volume 25 , Issue 4, 2017 January 16, {Pages 1352-1361 }

Abstract

In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these dual-quality compressors provide higher speeds and lower power consumptions at the cost of lower accuracy. Each of these compressors has its own level of accuracy in the approximate mode as well as different delays and power dissipations in the approximate and exact modes. Using these compressors in the structures of parallel multipliers provides configurable multipliers whose accuracies (as well as their powers and speeds) may change dynamically during the runtime. The efficiencies of these compressors in a 32-bit Dadda multiplier are evaluated in a 45-nm standard CMOS tec

RAP-CLA: A reconfigurable approximate carry look-ahead adder

Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram
Journal PaperIEEE Transactions on Circuits and Systems II: Express Briefs , Volume 65 , Issue 8, 2016 November 29, {Pages 1089-1093 }

Abstract

In this brief, we propose a fast yet energy-efficient reconfigurable approximate carry look-ahead adder (RAP-CLA). This adder has the ability of switching between the approximate and exact operating modes making it suitable for both error-resilient and exact applications. The structure, which is more area and power efficient than state-of-the-art reconfigurable approximate adders, is achieved by some modifications to the conventional carry look ahead adder (CLA). The efficacy of the proposed RAP-CLA adder is evaluated by comparing its characteristics to those of two state-of-the-art reconfigurable approximate adders as well as the conventional (exact) CLA in a 15 nm FinFET technology. The results reveal that, in the approximate operating mo

Hybrid redundancy approach to increase the reliability of FPGA based speed controller core for high speed train

Omid Akbari, Karim Mohammadi, Reza Omidi Gosheblagh
Journal PaperJournal of Electronics (China) , Volume 31 , Issue 3, 2014 June 1, {Pages 256-266 }

Abstract

With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger’s safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy (HDDR) method, the original controller is quadruplicated and correct values are voted through the comparator

A speed controller system based on FPGA for high speed train

O Akbari, K Mohammadi, R Omidi Gosheblagh
Journal Paper2nd International Conference on Recent Advances in Railway Engineering (ICRARE), Iran University of Science and Technology, Tehran, Iran , 2013 April 30, {Pages 07-Jan }

Recent advances in the automated control system of high-speed trains

O Akbari, K Mohammadi
Conference Paper2nd International Conference on Recent Advances in Railway Engineering (ICRARE), Iran University of Science and Technology, Tehran, Iran , 2013 April 30, {Pages 08-Jan }

Abstract

Current Teaching

  • MS.c.

    Dependable Systems Design

Teaching History

  • MS.c.

    Low - Power Digital Systems Design

  • MS.c.

    Reconfigurable Systems

  • 2020
    Azimi Sangdehi, Seyed Amir Hossein
    Managing the comfort level and energy consumption in smart buildings via Machine Learning
  • 2021
    Joorghanian, Fariba
  • Distinct PhD student in University of Tehran, Selected by Iran?s National Elites Foundation (INEF), 2018
  • Future Talent Guest Stay Award in TU Darmstadt, 2020
  • One Year Research Fellowship Award in Vienna University of Technology, Austria, 2017
  • Ranked 19th in PHD entrance exam of Iranian Universities, 2013
  • Ranked 2nd in B.Sc. among of 76 Electrical Engineering -Electronics Students, 2011
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